EDN

SP16160CH1RB High-IF Sub-sampling Receiver Subsystem Reference Design Kit

The SP16160CH1RB demonstrates a high-IF sampling receiver subsystem that provides signal amplification, digitization and clocking as used in wireless infrastructure systems. The subsystem includes the ...
EDN

Time-Interleaved ADCs for Digital Communication Receivers

In this paper, we describe the effects of timing and gain mismatches on the sampled signal in the general case of M-channel time-interleaved analog-to-digital converters (TI-ADCs) and propose a ...
Electronic Design

High-Speed Data Converters Make Direct-Sampling Receivers Practical

Communications receiver architecture has evolved slowly over the years. The most common and successful configuration is the superheterodyne architecture, which translates the incoming signal to a ...
Electronic Design

Fast ADC Facilitates Direct RF Sampling at Higher Frequencies

The critical component in all digital communications receivers is the analog-to-digital converter (ADC). The ADC sampling rate, bandwidth, and noise tolerance establishes the specifications and ...