Electronic Design

Development Environment Supports Mixed C++ And HDL Test Benches

TestBencher Pro v8.0 adds support for mixed C++ and hardware description language (HDL) test benches using the open standard TestBuilder library. This library offers useful verification capabilities, ...
Electronic Design

The MathWorks App Generates HDL Code From System Models

The Simulink HDL Coder automatically generates synthesizable hardware description language (HDL) code from models created in the company’s Simulink and Stateflow software. It produces ...
EDN

Test-bench generation tool simplifies IC design

TestBencher Pro VHDL and Verilog system-level test-bench generation software is said to dramatically simplify the process of creating and applying random bus transactions to RTL and gate-level IC and ...
EDN

Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code

HDL Coder generates target independent, synthesizable Verilog and VHDL code from MATLAB functions, Simulink models, and Stateflow charts. The generated HDL code is bit-true and cycle-accurate to ...
Semiconductor Engineering

Evaluation of LLMs on HDL-Based Communication Protocol Generation (U. of Illinois Urbana, CISPA)

A new technical paper titled “ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols” was published by researchers at University of Illinois Urbana Champaign and CISPA ...