College of Engineering and Mathematical Sciences | The University of Vermont
4:06
College of Engineering and Mathematical Sciences | The University of Vermont
Jan 1, 2009
uvm.edu
Cách tốt để viết transaction/sequence item trong môi trường UVM (VLSI verification): Transaction class là một object dùng làm stimulus đưa vào DUT. Sequence item được sequencer xử lý, rồi driver bắt tay (handshake) và lái tín hiệu xuống mức chân (pin-level) của DUT. Các hướng dẫn viết transaction class tốt: 1> Kế thừa từ `uvm_sequence_item 2> Chỉ random các trường đầu vào, không random đầu ra/response. Ví dụ: --->systemverilog rand bit [31:0] addr; rand bit [31:0] wdata; bit [31:0] rdata; 3> Đăn
0:05
Cách tốt để viết transaction/sequence item trong môi trường UVM (VLSI verification): Transaction class là một object dùng làm stimulus đưa vào DUT. Sequence item được sequencer xử lý, rồi driver bắt tay (handshake) và lái tín hiệu xuống mức chân (pin-level) của DUT. Các hướng dẫn viết transaction class tốt: 1> Kế thừa từ `uvm_sequence_item 2> Chỉ random các trường đầu vào, không random đầu ra/response. Ví dụ: --->systemverilog rand bit [31:0] addr; rand bit [31:0] wdata; bit [31:0] rdata; 3> Đăn
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